Abstract: As a leading contender of more-than-Moore technology, 2.5D/3D integrated circuits are built by stacking and connecting multiple chiplets with high-density inter-die vias. Heterogeneous integrated packaging is another promising solution to balance the performance, power, and cost tradeoff in processors, GPUs, FPGAs, and neural network accelerators. Such aggressive integration leads to many-fold improvements in interconnection length and design footprint. The industry is now working relentlessly to build advanced multi-chiplet packages that satisfy the ever-demanding memory bandwidth and energy efficiency requirements in datacenter servers, self-driving automobiles, and low-power mobile devices. However, the high-power devices packed under a small footprint raise various reliability concerns including power delivery, heat dissipation, and noise coupling. Advanced Computer-Aided Design (CAD) tools, algorithms, and models are essential to carefully analyze and efficiently address these challenging and complicated problems.
Another field that requires high-density and high-efficiency integration is power electronics. As a critical part of any electrical systems, power electronics design requires extensive knowledge of the device, circuit, package all the way to system and manufacturing. Designers need to understand electrical and thermal properties of materials, multi-physics design procedures, system control and optimization methodology, and the engineering art of design for manufacturability and reliability. Our research at the University of Arkansas targets both electrical and thermal issues altogether before an MCPM layout is finalized. A computer-aided design tool called PowerSynth is developed to further enrich the layout synthesis capability by introducing new algorithms and novel optimization methods for MCPM parasitic extraction, thermal modeling, heterogeneous integration, and reliability enhancement.
In this talk, I will present CAD and design techniques to enhance electro-power-thermal reliability of 2.5D and 3D ICs. First, I will introduce a CAD platform that evaluates and optimizes power and thermal reliability for 3D memory cubes and 3D multi-core processors. Next, I will present various methodologies for extracting and optimizing new parasitic elements in face-to-back and face-to-face 3D ICs as well as 2.5D wafer-level packages. I will conclude with our collaborative research with the NSF POETS center at the University of Arkansas on design automation for multi-chip power electronics. Our PowerSynth design automation platform integrates new modeling methods, heterogeneous components, 3D layouts, and pushes power electronics designs further toward high-power-density electronics systems enabling unprecedented productivity
Yarui Peng received the B.S. degree from Tsinghua University, Beijing, China in 2012. He earned his M.S. degree and Ph.D. in School of Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, USA in 2014 and 2016, respectively. He joined the Department of Computer Science and Computer Engineering at the University of Arkansas as an assistant professor in Jan. 2017. He also works with the NSF sponsored Engineering Research Center for Power Optimization of Electro-Thermal Systems (POETS-erc.org).
His research interests are in the areas of computer-aided design, analysis, and optimization for emerging technologies and systems, such as 2.5D and 3D ICs, high band-gap power electronics and systems, and high-efficiency digital designs and memory systems. He developed methodologies and algorithms for parasitic extraction, analysis and optimization for signal integrity, and alleviating reliability issues in thermal and power delivery in 2.5D and 3D ICs. He is also working on improving electro-thermal reliability in power systems such as multi-chip power modules (MCPMs). He is the recipient of best-in-session award in SRC TECHCON 14 and best student paper award in ICPT 16.
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